Digital computer systems have a history of continually increasing the speed of the processors used in the system. As computer systems have migrated towards multiprocessor systems, sharing information between processors and memory systems has also generated a requirement for increased speed for the off-chip communication networks. Designers usually have more control over on-chip communication paths than for off-chip communication paths. Off-chip communication paths are longer, have higher noise, impedance mismatches, and have more discontinuities than on-chip communication paths. Since off-chip communication paths are of lower impedance, they require more current and thus more power to drive.
When using inter-chip high-speed signaling, noise and coupling between signal lines (crosstalk) affects signal quality. One way to alleviate the detrimental effects of noise and coupling is through the use of differential signaling. Differential signaling comprises sending a signal and its complement to a differential receiver. In this manner, noise and coupling affect both the signal and the complement equally. The differential receiver only senses the difference between the signal and its complement as the noise and coupling represent common mode signals. Therefore, differential signaling is resistant to the effects that noise and crosstalk have on signal quality. On the negative side, differential signaling increases pin count by a factor of two for each data line. The next best thing to differential signaling is pseudo-differential signaling. Pseudo-differential signaling comprises comparing a data signal to a reference voltage using a differential receiver or comparator.
When high speed data is transmitted between chips, the signal lines are characterized by their transmission line parameters. High speed signals are subject to reflections if the transmission lines are not terminated in an impedance that matches the transmission line characteristic impedance. Reflections may propagate back and forth between driver and receiver and reduce the margins when detecting signals at the receiver. Some form of termination is therefore usually required for all highspeed signals to control overshoot, undershoot, and increase signal quality. Typically, a Thevenin's resistance (equivalent resistance of the Thevenin's network equals characteristic impedance of transmission line) is used to terminate data lines allowing the use of higher valued resistors. Additionally, the Thevenin's network is used to establish a bias voltage between the power supply rails. In this configuration, the data signals will then swing around this Thevenin's equivalent bias voltage. When this method is used to terminate data signal lines, a reference voltage is necessary to bias a differential receiver that operates as a pseudo-differential receiver to detect data signals in the presence of noise and crosstalk.
The logic levels of driver side signals are determined by the positive and ground voltage potentials of the driver power supply. If the driver power supply has voltage variations that are unregulated, then the logic one and logic zero levels of the driver side signals will undergo similar variations. If the receiver is substantially remote from the driver such that its power supply voltage may undergo different variations from the driver side power supply, then additional variations will be added to any signal received in a receiver side terminator (e.g., Thevenin's network). These power supply variations will reduce noise margins if the reference has variations different from those on the received signals caused by the driver and receiver side power supply variations.
When using pseudo-differential signaling for communicating between integrated circuit (IC) chips, the accuracy of the reference compare level (Vref) tends to be one of the large limiting factors in extending this reduced power and area signaling method to the multi-gigahertz frequency range. The variations in Vref due to process variations, package variations, and variations resulting from noise events, all contribute to tolerances that must be overcome by using a larger voltage swing. Reducing these tolerances may result in a pseudo-differential signaling bus design that may be used for signals in the 2–3 Gigahertz frequency range without resorting to larger signal swings and thus higher power and increased area.
The performance of a typical chip-to-chip communication interface is constrained by the finite bandwidth of the communication channel (the channel can be viewed as a low pass filter). As the signaling frequency increases, the increased attenuation of the highest frequency signal components causes the signal edges to be rolled off. This “spreading” of the signal edges also leads to increased inter-symbol (e.g., logic states on successive clock cycles) interference (ISI) where the energy from previous logic state(s) interferes with the presently asserted logic state. Edge roll off and ISI decrease timing and noise margins and prevent error free communication at higher frequencies.
Solving this bandwidth problem has involved the use of a pre-compensating driver that dynamically changes strength depending on the transmitted bit history. In essence, a stronger driver is used when the symbol pattern entails switching the signal's logic state (e.g., “0” to “1” or “1” to “0” transition), and a weaker driver is used when the symbol pattern requires no logic state changes between consecutive symbols. This solution inherently involves choosing a ratio of strong driver strength to weak driver strength (where strength is usually measured as the driver's output resistance). The circuit designer would typically choose an optimal ratio depending on the attenuation of the communication channel.
The optimal pre-compensation ratio depends on the communication channel, therefore, a circuit optimally tuned for one channel will likely perform sub-optimally on another channel having different attenuation characteristics. This is the problem with the previous solution: As the channel changes, the circuit designer must re-tune the driver circuit in order to achieve optimal performance. This is expensive as it requires (a) the engineer's time and (b) the cost to change the hardware.
There is, therefore, a need for a driver that allows the optimal performance of the driver to be programmable so that the optimal pre-compensation ratio for each driver for each channel path may be set under system control after chip design.